FPGA Project: Graphical LCD

First success with a new project: a simple frame buffer and controller for the graphical LCD display I’d previously used with an AVR.

The red board is a Papilio One with a Spartan 3E FPGA, power supply, SPI dataflash for the FPGA configuration, and a FTDI USB-serial IC for communications and programming. The white protoboard houses buffers to drive the 5V LCD from the 3.3V FPGA I/O and a MAX232 used to provide the awkward negative LCD drive voltage. To the left on the green protoboard is a 4-character dot matrix LED display.

A block RAM is just the right size to perform as a frame buffer, and they are dual-ported, so one port can be set aside for outside access. The frame buffer continuously cycles through the contents of that RAM with a simple state machine, occasionally wiggling control signals and delaying for a short period between each line to let the display react. The code will appear on GitHub when it’s cleaned up a bit.

edit: The code for the LCD controller/framebuffer is here.

5 comments

  1. costi says:

    I have a display (LRWBL4051A) led by (LC79401) AND another display (123K03551) led by (6 KS0104) and (3 KS0103) and fail to enable use an ATMEGA 16 or 32. far as I read can be activated only by (sed1330 or sed1335). you can help me with a code?
    pin out:
    frame
    cl1
    cl2
    on/off
    m

  2. cjh says:

    Working AVR code is linked in the previous postings, which also have a brief explanation of the function. This sort of thing can be hard to troubleshoot without an oscilloscope or logic analyzer, I really can’t be of much more help than that with so little information.

    One thing that comes to mind is that controlling one of these displays is a real-time problem. You must select a line, load the data for it, and wait a fixed amount of time for the LCD to respond before moving on to the next line, and continuously repeat this process to keep the display refreshed. You can’t just blast data at the LCD and get useful results. You also must toggle the frame line each frame to get a clear picture and avoid damage to the display.

  3. costi says:

    thanks.

  4. Ola says:

    Nice going! I happened to have the same situation as you: a couple of eg2401 lying around, knowing that it’s hard to get them going, but still they’re quite nice displays. I also have some boards with epson driver “E-1330” that I guess is equiv. To SED1330, still, I think using these would be to hard (willing to sell). However, I looked at your vhdl test, but couldn’t find port/pin mappings for the fpga. Are these described in some of the libraries used? I’m also interested in putting a controller in a programmed chip (cpld?). What would you recommend there? (I’ve done just a little vhdl, so please be gentle :-)
    Would appreciate some clearification (by email maybe?).

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